Electronic Experiences in a Virtual Lab by Roberto Gastaldi & Giovanni Campardo

Author:Roberto Gastaldi & Giovanni Campardo
Language: eng
Format: epub
ISBN: 9783030451790
Publisher: Springer International Publishing

Figure 5.12 also shows the signal CKA which is the intermediate reference obtained by dividing the 50 Hz power supply by five.

The simulation shown in Fig. 5.12 covers more than 2 s and you can see correctly two pulses of CKin, but the simulation has been performed considering also the power-on of the circuit.

From the figure you can see the signal REF (remember that it is the result of squaring the 50 Hz power supply) which needs to be divided by fifty to obtain a pulse per second that the amplitude of the input pulse (purple line) to the divide-by-50 stage follows the ramp-up of the internal supply voltage provided by the regulator circuit. You can also see that the reset signal (red line) keeps all the counter of the system blocked until the internal supply voltage has reached its steady-state value, then counting starts after reset signal has gone low. This is very important to avoid malfunction during the count operation.

The last circuit we need to analyze to finish the analysis of the CKGEN block is highlighted by a blue line and must generate a reset signal at the start-up of the clock , or in other words when we switch on the power to the system. This is necessary to avoid an incorrect positioning of all the counters. Such a circuit is very common in logic design and it is called power-on reset. It is apparently very simple but it may be the source of a number of failures because its tuning is very critical. Actually, it must generate a signal only when the power supply has reached its steady-state value, not too early otherwise the power supply will be too low and still moving and more important reset signal must be generated in a reliable way, which means always when it is needed regardless tolerance of electronic components, operation temperature and power supply variations.

The key components are C8 and R16 in the schematic of Fig. 5.10. At power-up, the intermediate node between these two components is tight to ground because of the discharged capacitor . The NAND device U6A connected as an inverter causes the reset signal to be high, but when the capacitor charges following Vcc grow-up the reset signal is turned low thus enabling the whole system. The important point is to choose the RC time constant in such a way that the inverter threshold is reached when Vcc is over 4.0 V ensuring a safe operation voltage. You can see this behavior looking at simulation in Fig. 5.13.

Fig. 5.13Relevant waveforms of power-on reset circuit

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